AN4031 datasheet(16/36 Pages) STMICROELECTRONICS

16 / 36 page

DMA controller description

AN4031

16/36

DocID022648 Rev 1

the status register (DMA_LISR and DMA_HISR) from the previous data block DMA

transfer should be cleared before the stream can be re-enabled.

Set the peripheral port register address in the DMA_SxPAR register. The data will be

moved from/to this address to/from the peripheral port after the peripheral event.

Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R

this memory after the peripheral event.

Configure the total number of data items to be transferred in the DMA_SxNDTR

decremented.

Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.

If the peripheral is intended to be the flow controller and if it supports this feature, set

the PFCTRL bit in the DMA_SxCR register.

Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.

Configure the FIFO usage (enable or disable, threshold in transmission and reception).

Configure the data transfer direction, peripheral and memory incremented/fixed mode,

single or burst transactions, peripheral and memory data widths, Circular mode,

Double-buffer mode and interrupts after half and/or full transfer, and/or errors in the

DMA_SxCR register.

10. Activate the stream by setting the EN bit in the DMA_SxCR register.

As soon as the stream is enabled, it can serve any DMA request from the peripheral

connected to the stream.

AN4031 bảng dữ liệu(PDF) 16 Page - STMicroelectronics