Low-inductance capacitor layout in high-frequency applications

AN3317

20/22

Doc ID 18249 Rev 2

A.2

0402 package low inductance layout

Figure 2 shows a low inductance layout for a 0402 decoupling capacitor using 2 vias with a

10 mil drill size. Note that:

●

Vias are placed close to the lands.

●

Vias of opposite polarity are place close together.

●

The trace connecting land to via is wide.

Figure 7.

0402 package low inductance layout

Table 5.

0402 packages low inductance layout dimensions

Dimension

Distance (mil)

D (land to hole)

1.

The land to hole separation is determined by the PCB fabrication tolerances.

E (hole to hole)

2.

Minimize this distance, consistent with PCB fabrication tolerances. If the capacitor is placed within a BGA

ball field, make dimension E the same as the ball pitch.

F (trace width)

20