DDR memory interface

AN3317

12/22

Doc ID 18249 Rev 2

Fly-by topology routes A/C/C signal groups in a daisy chain fashion, with terminations on

all signals after the last DRAM device. Data lane slices are routed to individual DRAM

devices.

Balanced T topology can be used for A/C/C signal groups if only two memory devices are

used.

Figure 2.

Routing topologies

5.3.4

Data signal routing

To simplify the routing of the data signals, it is possible to swap data between data slices.

But it is mandatory to route and connect the SPEAr DDR_DQ0 (ball AF2), DDR_DQ8 (ball

AH3) DDR_DQ16 (ball AE8) and DATA24 (ball AH9) on each LSB DDR data pin.

Table 1.

Trace length matching guidelines, balanced-T configuration

Parameter

Description

Maximum

Unit

L1+L2, L1+L3 length matching for all signals

15

ps

|L2-L3| length matching tolerance of branches

30

ps

ADDR/CON/COM

DQ[15:0]

DQ[31:16]

DQ[ECC]

DQ[15:0]

DQ[31:16]

Termination

Fly-by topology

ADDR/CON/COM

Equal length

L1

Balanced T topology

L2

L3

SPEAr1340

SPEAr1340