DDR memory interface

AN3317

14/22

Doc ID 18249 Rev 2

5.4

Return path integrity

To minimize signal delays, significant crosstalk, and timing violations, a continuous path for

return current must exist for all DRAM signals.

To simplify return paths, route all signals referenced to a ground plane.

Do not route any DDR3 signals on top of split planes or copper voids.

For traces routed near the edge of a reference plane, keep a minimum of 30 mil between the

trace and the edge of the reference plane.

Signal layer changes

The preferred location for layer change vias is near the signal ball under a device, either

DRAM or SPEAr, enabling a signal return path through the device ground vias and

decoupling capacitors.

If layer changes through a via to a different reference plane are necessary away from the

devices:

●

Provide the layer transitions a nearby path for return current.

●

If both layers are ground, place a return path ground via less than 1 mm from the signal

via.

●

Avoid sharing return current vias; each signal via should have its own nearby return via

(ground via). If multiple signals change layers in close proximity:

–

Provide each signal via its own return current via.

–

Use a stagger pattern to separate signal vias (and their return current vias) from

other signal vias.

–

If routing density prevents a stagger pattern, add as many ground vias as possible

among the signal vias.

5.5

Vref routing

Provide an accurate and quiet Vref to both the dram and the controller. Because of the slope

of the signal, a noisy Vref effectively introduces jitter, which can be a significant source of

jitter-caused timing errors.

Vref is generated by a precision voltage divider.

Recommended: Use 0.1% tolerance resistors.

Place a decoupling capacitor very close (within 1 mm) to the Vref balls.

Use good capacitor layout techniques. Place the voltage divider resistors close to the DRAM

device to minimize trace length, but not so close that they interfere with other critical signal

or power routing.

Do not route the Vref trace near noisy traces or planes.

Do not place a decoupling capacitor at the junction of the resistors – only at the Vref balls.

If the Vref trace length must be long, make the divider resistor value close to 2x the

characteristic impedance of the Vref trace; 150

much power. If a long trace, noise coupling, or both is unavoidable between the DRAM and

the controller, it is preferable to generate a separate Vref for the DRAM and the controller.