AN2784

Interfacing with an 8-bit NAND Flash memory

Doc ID 14779 Rev 4

27/31

The error correction code algorithm implemented in the FSMC can perform 1-bit and 2-bit

error detection per page read from or written to the NAND Flash memory. It is based on the

Hamming algorithm and consists in calculating the row and column parity.

4.4.2

Error detection

Figure 12.

Error detection flowchart

When an error occurs during the write operation, this error is either correctable or

uncorrectable depending on the ECC XOR operation:

●

Case of a correctable error

The ECC XOR operation contains 11-bit data at 1. And each pair parity is 0x10 or

0x01.

●

Case of an ECC error

The ECC XOR operation contains only one bit at 1.

●

Case of an uncorrectable error

The ECC XOR operation is random data. In this case the page data cannot be

corrected.

Based on the flowchart shown in Figure 12, the correction software is easy to implement.

The first step consists in detecting whether an error occurred during the write operation. If

that was the case, the second step consists in determining if the error is correctable or not. If

it is correctable, then the third step consists in correcting the error.

The error correction is based on the second ECC generated after the read operation. The

error location can be identified from this code. Usually, the following data are extracted from

the ECC:

P1024, P512, P256, P128, P64, P32, P16, P8, P4, P2, P1, where Px are the line and

column parity.

In case of an 8-bit memory, P4, P2, P1 define the error bit position. And P1024, P512, P256,

P128, P64, P32, P16, P8 define the error byte position.

Program NAND page operation successful

Read ECC value during Program operation

Read written NAND page

Read new ECC value during Read operation

XOR operation between the two ECC values

All ECC bits

are zero

Yes

No

No error

Error detected

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