AN2784 datasheet(25/31 Pages) STMICROELECTRONICS

25 / 31 page

AN2784

Interfacing with an 8-bit NAND Flash memory

Doc ID 14779 Rev 4

25/31

Using the above described formulas, the memory timings in Table 7 and the

STM32F10xCDE FSMC asynchronous timings in Table 2, we have:

●

Setup time: 0x0

●

Wait time: 0x2

●

Hold time: 0x1

●

HiZ time: 0x0

4.3

Hardware connection

Table 8 gives the correspondence between the NAND Flash memory pins and the FSMC

pins and shows the GPIO configuration for each FSMC pin.

In case of a 16-bit NAND Flash memory, the data/address bus is 16 bits wide and the

remaining FSMC data/address bus are used.

tRP

Read Enable low to Read Enable high

tCS

Chip Enable low to Write Enable high

tALS

AL setup time

tCLS

CL Setup time

tCH

E Hold time

tALH

AL Hold time

tCLH

CL Hold time

tDS

Data Valid to Write Enable high

tWC

Write Enable low to Write Enable low

tRC

Read Enable low to Read Enable low

tREA

Read Enable low to Output Valid

Table 7.

NAND512W3A2C Flash memory timings (continued)

Symbol

Parameter

Value

Unit

Table 8.

NAND512W3A signal to FSMC pin correspondence

Memory signals FSMC signals

Pin / Port

assignment

Pin / Port

configuration

Signal description

ALE/A17

PD11

AF push-pull

Address Latch Enable

CLE/A16

PD12

AF push-pull

Command Latch Enable

I/O0-I/O7

D0-D7

Port D/Port E

AF push-pull

Data D0-D7

NCE2

PD7

AF push-pull

Chip Enable

NOE

PD4

AF push-pull

Output Enable

NWE

PD5

AF push-pull

Write Enable

NWAIT/INT2

PD6/PG6

Input pull-up

Ready/Busy signal

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