AN2647 datasheet(29/34 Pages) STMICROELECTRONICS

29 / 34 page

AN2647

Interfacing with synchronous memory

29/34

Enable synchronous mode

Enable BCLK clock

Enable burst read and write

Burst read data transfer length

Burst write data transfer length

Table 10.

EMI and port register config. for PSRAM sync mode (80 MHZ) BCLK)

EMI configuration

Multiplexed 16-bits asynchronous mode

Bit

Name

Bit

value

Function

EMI_BCRx (maintain

reserved bits' default

value)

19:18

BWLEN

Burst write transfer length: Continuous

Burst

SYNCWRITEDE

synchronous write device

BMWrite

Burst mode write enabled

11:10

BRLEN

Burst read transfer length: Continuous

Burst

SYNCREADDEV

synchronous read device

BPM

Burst mode read

5:4

16-bit data bus width

Bank not write protected

BLE

Byte Lane Enable

EMI_RCR

4:0

WSTRD

101

Read Wait State = 5

70 ns PSRAM access time

EMI_OECR

3:0

WSTOEN

100

EMI_RDn assertion delay =4

EMI_WCR

4:0

WSTWR

101

Write Wait State =5

EMI_WECR

3:0

WSTWEN

000

EMI_WRn assertion delay =0

EMI_ICR

3:0

IDCY

011

Idle Cycle = 3 BCLK

EMI_BRDCR

4:0

WSTBRD

000

Burst read wait state=0

SCU_EMI

BYTE_EN

Enable EMI_UBn and LBn signals

BCLK_EN

Enable BCLK output

GPIOEMI

Set Port 8/9 as EMI bus

SCU_CLKCNTR

18:17

EMIRatio

BCLK=HCLK (80 MHz)

SCU_SCR0

EMI_ALE_LNGT

ALE length=1.5 tBCLK

EMI_ALE_POLR

ALE polarity-active low

EMI_MULTIPLE

XED

Multiplexed mode

SCU_GPIOTYPE [5:9]

7:0

Push-pull

0x00

Configure Port 5,6,7,8 and 9 as push-

pull

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