AN2647 datasheet(17/34 Pages) STMICROELECTRONICS

17 / 34 page

AN2647

Interfacing with asynchronous memory

17/34

1.2.4

Memory bank read and writing timings

The EMI supports 4 external memory banks, up to 64Mbyte in each bank. Depending on the

address in the current bus cycle, the EMI activates one of the 4 chip selects (CS0-CS3) to

select the targeted device.

Every memory bank has its own set of bus configuration registers and therefore is

configured to have its own set of bus timing as well. Usually high speed device like SRAM

resides in one bank while slow Flash memory and I/O device reside in another bank. Bus

timing can be switched dynamically from one bank to the other bank.

1.3

EMI bus configuration examples

Table 5 lists all the configuration registers and control bits that you need to configure the

EMI bus for asynchronous mode. The multiplexed mode example is configured for the 10ns,

16-bit SRAM (IS61LV25616AL) in Figure 2. The non-multiplexed mode example is

configured for the 20ns, 8-bit SRAM (C1019CV33) in Figure 6. The timings in Table 5 are

based on a 96 MHz BCLK clock.

Table 5.

EMI Bus configuration examples for asynchronous memory devices

Configuration

Multiplexed 16-bit bus

Non-Multiplexed 8-bit bus

Bit

Name

Bit

value

Function

Bit

value

Function

EMI_BCRx

SYNCWRITEDEV

Asynchronous

write device

Asynchronous write

device

SYNCREADDEV

Asynchronous

read device

Asynchronous read

device

BPM

Normal mode

(non-burst or page

mode)

Normal mode (non-

burst or page mode)

5:4

16-bit data bus

width

8-bit data bus width

3WP

Bank not write

protected

Bank not write

protected

EMI_RCR

4:0

WSTRD

Read Wait State

10 ns access time

Read Wait State

20 ns access time

EMI_OECR

3:0

WSTOEN

EMI_RDn

assertion delay

EMI_RDn assertion

delay

EMI_WCR

4:0

WSTWR

Write Wait State

EMI_WECR

3:0

WSTWEN

EMI_WRn

assertion delay

EMI_WRn assertion

delay

EMI_ICR

3:0

IDCY

Idle Cycle = 3

BCLK

Idle Cycle=3 BCLK

EMI_BRDCR

4:0

WSTBRD

Burst read wait

state=0

Burst read wait state=0

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