AN2647 datasheet(9/34 Pages) STMICROELECTRONICS

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AN2647

Interfacing with asynchronous memory

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EMI_WR signal configuration

The EMI_WRxn timings are controlled by the WSTWR value in the EMI_WCRxn register

(Write Wait State Control) and the WSTWEN value in the EMI_WECRx (Write Enable

Control) register.

●

WSTWEN: Write Enable. WSTWEN specifies the delay period between the assertion

of the CSx chip select and the falling edge of EMI_WRxn. The delay is defined in terms

of BCLK clock periods which is (WSTWEN + 1/2) for asynchronous write cycles. The

minimum WSTWEN value is 1 in a multiplexed bus (for ALE with one BCLK period

width).With WSTWEN=1, EMI_WRxn becomes active only after the address phase is

over.

●

WSTWR: Write wait state. WSTWR specifies the pulse width of EMI_WRx. The pulse

width is defined in terms of BLCK periods and is equal to (WSTWR-WSTWEN+1) for

asynchronous write cycles.

The choice of the WSTWEN and WSTWR values depend on the address and data setup

time and data hold time of the memory device. The STR9 provides at least 1.5 tBCLK of

address setup time with WSTEN=1; and by default 0.5 tBCLK of data and address hold time.

The WSTWR or pulse width is then set accordingly to meet the data setup time of the

memory device

The write bus cycle in Figure 4. provides address setup time of 2.5 *tBCLK, data setup time

of 1*tBCLK and 0.5*tBCLK of data hold time.

Byte and word access in 16-bit multiplexed mode

The previous sections describe the read and write timings for 16-bit or half word access.

The CPU can generate 8-bit or 32-bit access using the assembly instruction of STRB, LDRB

or STR, LDR. The 8-bit bus cycle is the same as the 16-bit bus cycles, except AD15-AD8

are not driven during the data phase of the cycle.

For a 32-bit access, the EMI generates two consecutive 16-bit bus cycles. The two bus

cycles are identical to the standard 16-bit cycle, the only difference is the EMI_CS chip

select signal stays low during the two write cycles. Figure 5. shows the bus timings when the

CPU executes a 32-bit STR instruction followed by a LDR instruction. Note the EMI_CS

signal stays low in the two write bus cycles, but are separated in the two read bus cycles.

The two half words that were read in the two LDR read cycles are combined into one word in

the EMI block before being transferred to the CPU.

Figure 5.

Word (32-bits) write and read bus cycles in 16-bit multiplexed mode

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