AN1014 datasheet(23/25 Pages) STMICROELECTRONICS

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HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

– Slow mode is selected with the divided external clock factor equal to 64. This clock (fCPU)

drives the active peripherals (WDG and LT-Realtime Clock) and the core when it is active.

In the Main Clock Control/Status Register (MCCSR) the SMS bit must be set.

– All I/O ports are connected to an external pull-up or pull-down to avoid leakage due to floating

inputs.

– The Watchdog Timer (WDG) is active with a 2msec time-out period.

– Here 8 bit LT is used to wake-up the core at regular intervals, 1msec, to avoid a WDG reset.

– In LTCSR register set, TB to 0 & TBIE to 1.

– The main loop contains a Wait For Interrupt “WFI” instruction.

– Here all other peripherals (except above) are OFF

– Set Option Byte “value” to “FC FE” (In Option Byte, PLL = disabled, RC Oscillator = OFF,

LVD = OFF, WDG SW = Software, WDG HALT= No Reset when Halt)

– For the ST7 software configuration, please refer to your datasheet.

Figure 6. Hardware Setup

7.3.2 Application

Methodology: An external CLK source, up to 16MHz is used on pin CLKIN. PLL is disabled

and internal RC Oscillator is OFF. So, fOSC is CLKIN / 2. All peripherals are in reset configura-

tion and the SMS bit in the MCCSR is set to 1.Hence fCPU is fOSC/32. All I/O ports are con-

nected to an external pull-down.

Measurements:

The measurement of current (IDD) is done directly on the VDD pin. The microcontroller is in

Wait mode and is configured as described above, with the WDG and LT Timer active.

The values given in Table21 correspond to typical measured values. They are not maximum

or minimum values.

VDD

ST7LITE0

VDD

VSS

Port A, Port B

RDOWN

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