AN1014 datasheet(13/25 Pages) STMICROELECTRONICS

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HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

6.2.2.3 Halt Mode

Methodology: A resonator oscillator is used with fosc at 8 MHz. PLL*2 is disabled. So, fosc2 is

fosc/2. All peripherals are in reset configuration except the ports. The IS21 bit in the EICR is

cleared and the IS20 bit in the EICR is set to 1. All ports are set as Push-Pull Outputs with low

level except PF1 (which is used for charging and discharging the capacitor).

Measurements:

Table 10. Consumption IDD (Halt Mode) for Cext = 1 uF at TA = + 25 °C

6.2.3 Conclusion

If VDD increases, RPU decreases. So, the RC time constant also decreases for a fixed value of

Cext. So, the wake-up time decreases. Hence the wake-up frequency increases with the in-

crease of VDD.

A delay after wake-up by an interrupt exists only in Halt mode, because in all other low power

modes (except Halt mode) the oscillator is ON. So, to wake up from HALT mode, the MCU

needs 256/4096 CPU cycles delay for the oscillator startup, during this time it consumes some

current.

* Wake-Up frequency is the external interrupt frequency (Wake-Up time is the time after which

the MCU is woken up from the different modes (Wait, Slow-Wait, Active-Halt, Halt)).

6.3 EXAMPLE 3: APPLICATION WITH PERIODIC WAKEUP AND WATCHDOG

For this example, we assume that for the application the Watchdog Timer (WDG) has to re-

main active and that the microcontroller has to stay in low power mode for an undefined time

period. Therefore, Halt mode can not be used, as the “Halt” instruction resets the microcon-

troller when the WDG is active and WDGHALT option bit in the option byte is set to 1. When

the WDGHALT option bit in the option byte is 0 and WDG is active, a “Halt” instruction doesn’t

generate a Watchdog reset. In this case, the MCU enters Halt mode. The Watchdog counter

is decremented once and then stops counting and is no longer able to generate a watchdog

reset until the MCU receives an external interrupt or reset. Active-Halt mode can also not be

used, because, the device cannot spend more than a defined period in this power saving

mode. Consequently, Wait mode is used, associated with Slow mode configured for the

slowest frequency. This slow mode clock (fCPU) drives the active peripherals and the CPU

when it is woken-up. Of course, to reduce power consumption further, Halt mode should be

used wherever possible.

In terms of applications, users usually try to optimize the power consumption during the wait

loop in the main program. In this configuration the microcontroller is mostly idle, waiting for an

fOSC(MHz)

IDD at VDD = 4.5 V

IDD at VDD = 5 V

IDD at VDD = 5.5 V

360

µA580 µA

840

µA

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