AN2960 datasheet(39/41 Pages) STMICROELECTRONICS

39 / 41 page

AN2960

Application information

Doc ID 15557 Rev 1

39/41

9.8

DataReady vs. interrupt signal

The device includes two pins which can be activated to generate either the DataReady or

the interrupt signal. The functionality of the pins is selected by setting the interrupt

configuration bits located in CTRL_REG3(2-0) for interrupt pin 1 (INT1) and in

CTRL_REG3(5-3) for interrupt pin 2 (INT2), in accordance with the block diagram given in

Figure 16.

The DataReady signal stored in STATUS_REG(3), which indicates when a new set of

acceleration data is ready, is made available by setting the cfg bit to 100. The interrupt

source 1 signal is sent to the pin when the cfg bit is set to 001 and the interrupt source 2

when the cfg bit is set to 010. A logic “OR” combination of interrupt source 1 and 2 can be

sent to an interrupt pin by writing 011 in the cfg bit.

Figure 16.

Interrupt and DataReady signal generation block diagram

The DataReady signal rises to 1 when a new set of acceleration data has been generated

and is available for reading. The signal is reset after all the enabled channels are read

through the serial interface.

Figure 17.

DataReady signal

CTRL_REG3(2,1,0)

INT1 signal

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 1 1

Free-Fall,

Wake-Up

Interrupt

Counter

Clock (100/400Hz)

ff_wu_duration

Latch

FF_WU_CFG1(LIR)

Generator

DataReady signal

DataReady

Signal

Generator

Interrupt Generator

(FF_WU_1, 2)

(FF_WU_SRC_1)

(FF_WU_SRC_2)

Latch

FF_WU_CFG2(LIR)

Free-Fall,

Wake-Up

Counter

Clock (100/400Hz)

ff_wu_duration

CTRL_REG3(5,4,3)

INT2 signal

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 1 1

RDY

DATA READ

ACCEL DATA

Accel. Sample #(N)

Accel. Sample #(N+1)

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