AN2960 datasheet(12/41 Pages) STMICROELECTRONICS

12 / 41 page

Digital interfaces

AN2960

12/41

Doc ID 15557 Rev 1

Transfer when master is receiving (reading) multiple bytes of data from slave

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes per transfer is unlimited. Data is transferred with the most significant bit (MSb) first.

If a receiver cannot receive another complete byte of data until it has performed some other

function, it can hold the clock line SCL low to force the transmitter into a wait state. Data

transfer continues only when the receiver is ready for another byte and releases the data

line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive

because it is performing some other real-time function) the data line must be left high by the

slave. The master can then abort the transfer. A low to high transition on the SDA line while

the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated

by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of the first register to read.

In the communication format presented, MAK signifies master acknowledge and NMAK is

no master acknowledge.

4.1.2

I2C subsequences

In order to better define subsequences and to clarify line SCL and SDA behavior, a

description containing the discrete values of SCL and SDA follow. These simple

subsequences are used to implement the complex commands described in the following

paragraph.

Master

SAD + W

SUB

SAD + R

MAK

Slave

SAK

DATA

Master

MAK

NMAK

Slave

DATA

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