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AN2960

Free-fall and wake-up registers

Doc ID 15557 Rev 1

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This register keeps track of the acceleration event triggering (or that has triggered, if the LIR

bit in FF_WU_SRC_1 reg is set to 1) the interrupt signal. In particular, IA is equal to 1 when

the combination of acceleration events specified in FF_WU_CFG_1 register is true. This bit

is used for the generation of the interrupt signal associated with free-fall/wake-up events.

X, (Y, Z) high is true when the module of the acceleration value of the X (Y, Z) channel is

higher than the preset threshold which is defined as the concatenation of FF_WU_THS_1.

Similarly, X, (Y, Z) low is true when the module of the acceleration value of the X (Y, Z)

channel is lower than FF_WU_THS_1.

Reading at this address clears the FF_WU_SRC_1 register and the FF_WU1 interrupt and

allows the refreshment of data in the FF_WU_SRC_1 register itself, if the latched option was

chosen.

8.4

FF_WU_THS_1 (32h)

Free-fall, wake-up threshold for interrupt 1.

The DCRM bit allows selection of the way in which the duration counter is reset. When

DCRM is ‘0’, the duration counter is reset immediately whenever the internal inertial event

programmed by the user is not active (Figure 12 part B) while it is decremented when

DCRM is set to 1 (Figure 12 part C). The latter configuration allows the filtering out of

spurious spikes which might impair the recognition and validation of inertial events.

DCRM

THS6

THS5

THS4

THS3

THS2

THS1

THS0

DCRM

Duration counter reset mode selection. Default value: 0

(0: counter reset; 1: counter decremented)

THS6, THS0

Free-fall / wake-up threshold: default value: 000 0000

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