28F016SA datasheet(41/55 Pages) INTEL

41 / 55 page

28F016SA

NOTES:

CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

Read timings during data program and block erase are the same as for normal read.

Refer to command definition tables for valid address and data values.

Sampled, but not 100% tested.

Data program/block erase durations are measured to valid Status Register data.

Word/byte program operations are typically performed with 1 programming pulse.

Address and data are latched on the rising edge of WE# for all command write operations.

This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office

for more information.

WE# (W)

OE# (G)

RP# (P)

CEx # (E)

(V)

DEEP

POWER-DOWN

ADDRESSES (A)

WHEH

ELWL

WHDX

WHWL

WLWH

DVWH

PHWL

HIGH Z

QVVL

PPH

VPWH

READ EXTENDED

STATUS REGISTER DATA

DATA (D/Q)

WHQV1,2

WRITE DATA-WRITE OR

ERASE SETUP COMMAND

WRITE VALID ADDRESS

& DATA (DATA-WRITE) OR

ERASE CONFIRM COMMAND

AUTOMATED DATA-WRITE

OR ERASE DELAY

RY/BY# (R)

WHRL

WHGL

ADDRESSES (A)

AVAV

AVWH

WHAX

READ COMPATIBLE

STATUS REGISTER DATA

WRITE READ EXTENDED

A=RA

NOTE 1

NOTE 2

NOTE 3

NOTE 4

OUT

RHPL

GHWL

NOTE 5

PPL

AVAV

AVWH

WHAX

0489_14

NOTES:

This address string depicts data program/block erase cycles with corresponding verification via ESRD.

This address string depicts data program/block erase cycles with corresponding verification via CSRD.

This cycle is invalid when using CSRD for verification during data program/block erase operations.

CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

RP# low transition is only to show tRHPL; not valid for above read and program cycles.

Figure 15. AC Waveforms for Command Write Operations

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