Integrated

Circuit

Systems, Inc.

ICS9250-23

Third party brands and names are the property of their respective owners.

Block Diagram

9250-23 Rev A 4/3/01

Pin Configuration

Recommended Application:

810/810E type chipset

Output Features:

•

2 - CPUs @ 2.5V, up to 166MHz.

•

13 - SDRAM @ 3.3V, up to 166MHz.

•

2 - 3V66 @ 3.3V, 2x PCI MHz.

•

8 - PCI @3.3V.

•

1 - 48MHz, @3.3V fixed.

•

1 - 24MHz @ 3.3V

•

2 - REF @3.3V, 14.318MHz.

Features:

•

Up to 166MHz frequency support

•

Support power management through PD#.

•

Spread spectrum for EMI control (± 0.25%)

center spread.

•

Uses external 14.318MHz crystal

•

FS pins for frequency select

Key Specifications:

•

CPU Output Jitter: <250ps

•

IOAPIC Output Jitter: <500ps

•

48MHz, 3V66, PCI Output Jitter: <500ps

•

Ref Output Jitter. <1000ps

•

CPU Output Skew: <175ps

•

PCI Output Skew: <500ps

•

3V66 Output Skew <175ps

•

For group skew timing, please refer to the

Group Timing Relationship Table.

Frequency Generator & Integrated Buffers for Celeron & PII/III™

56-Pin 300 mil SSOP

1. These pins will have 2X drive strength.

* 120K ohm pull-up to VDD on indicated inputs.

Power Groups

GNDREF, VDDREF = REF, Crystal

GND3V66, VDD3V66 = 3V66

GNDPCI, VDDPCI = PCICLKs

GNDCOR, VDDCOR = PLLCORE

GND48, VDD48 = 48

GNDSDR, VDDSDR = SDRAM

GNDLCPU, VDDLCPU = CPUCLK

GNDLPCI, VDDLAPIC = IOAPIC

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.