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ICS9250-23 bảng dữ liệu(PDF) 9 Page - Integrated Circuit Systems |
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ICS9250-23 bảng dữ liệu(HTML) 9 Page - Integrated Circuit Systems |
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9 / 15 page ![]() 9 ICS9250-23 Third party brands and names are the property of their respective owners. Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C p u o r G z H M 6 6 U P Cz H M 0 0 1 U P Cz H M 3 3 1 U P C t e s f f Oe c n a r e l o Tt e s f f Oe c n a r e l o Tt e s f f Oe c n a r e l o T M A R D S o t U P Cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 V 3 o t U P Cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 V 3 o t M A R D Ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 I C P o t 6 6 V 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 T O D & B S Uh c n y s AA / Nh c n y s AA / Nh c n y s AA / N Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2V DD+0.3 V Input Low Voltage V IL V SS-0.3 0.8 V Input High Current I IH V IN = VDD -5 5 µA Input Low Current I IL1 V IN = 0 V; Inputs with no pull-up resistors -5 µA Input Low Current I IL2 V IN = 0 V; Inputs with pull-up resistors -200 µA Operating I DD3.3V Cl = 0 pF; Select @ 66M 119 280 Supply Current I DDL2.5V Cl = 0 pF; Select @ 66M 3 25 Power Down Current I DD3.3VPD Cl = 0 pF; With Input to Vdd or Gnd 600 µA Input frequency F i V DD = 3.3 V 14.318 MHz Input Capacitance 1 C IN Logic Inputs 5 pF C INX X1 & X2 pins 27 45 pF Transition Time 1 T Trans To 1st crossing of target Freq. 3 ms Settling Time 1 T S From 1st crossing to 1% target Freq. 1 3 ms Clk Stabilization 1 T Stab From V DD = 3.3 V to 1% target Freq. 3 ms T PZH,TPZL output enable delay(all outputs) 1 10 ns T PHZ,TPLZ output disable delay(all outputs) 1 10 ns 1Guaranteed by design, not 100% tested in production. mA Delay 1 |
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