AT697F_14 datasheet(3/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

Refer to section “Differences between AT697F and AT697E” for detailed description of

the differences between AT697F and AT697E.

Figure 1. AT697 Block Diagram

AT697

SRAM

Flash

Interrupt

Controller

interrupt

FPU

AMBA

bridge

AMBA

Controller

Watchdog

Memory

Controller

PCI

RS232

JTAG

DSU

Timers

Clock

Generator

Reset

D-Cache

I -Cache

PCI/AMBA

bridge

AHB

APB

Integer Unit

(SPARC V8)

SDRAM

BRDY*

READ

WRITE*

A[27:0]

D[31:0]

...

PIO

config

IOs

RxD

TxD

RxD

TxD

RESET*

CLK

WDOG*

...

BYPASS

...

TDI

TDO

...

Pin Description

A signal name ending with a ‘*’ (e.g OE*) designates an active-low signal.

A bit field in a register are represented in a "dot" notation: MCFG2.ramwws is read as the

ramwws field in register MCFG2.

System Interface

RESET* - Processor reset (input)

When asserted, this asynchronous active low input immediately halts and resets the

processor and all on-chip peripherals. The processor restarts execution after the 5th ris-

ing edge of the clock after RESET* was de-asserted.

ERROR* - Processor error (open-drain output with pull-up)

This active low output is asserted when the processor is halted in error mode.

WDOG* - Watchdog timeout (open-drain output with pull-up)

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