AT697F_14 datasheet(13/176 Pages) ATMEL

13 / 176 page

AT697F

7703E–AERO–08/11

To execute instructions at a rate approaching one instruction per clock cycle, the IU

employs a five-stage instruction pipeline that permits parallel execution of multiple

instructions.

•

Fetch

The instruction is fetched from the instruction cache is enabled and available or the

fetch is forwarded to the memory controller.

•

Decode

The instruction is placed in the instruction register and decoded. The operands are

read from the register file and/or from immediate data and the next instruction

computed CALL/Bicc target address are generated.

•

Execute

Arithmetic, logical and shift operations are performed and the result saved in

temporary registers. Memory and JMPL/RETT target address are generated.

Pending traps are prioritized and internal traps are taken, if any.

•Memory

On a memory load instruction, data is read from the data cache if enabled and

available or the read is forwarded to the memory controller. On a memory store

instruction, store data is always forwarded to the memory controller and any

matching data cache entry is invalidated if enabled.

•Write

The result of any arithmetic, logical, shift or memory/cache read operation is written

back to the register file.

All five stages operate in parallel, working on up to five different instructions at a time.

A basic "single-cycle" instruction enters the pipeline and completes in five cycles. By the

time it reaches the write stage, four more instructions have entered and are moving

through the pipeline behind it. So, after the first five cycles, a single-cycle instruction

exits the pipeline and a single-cycle instruction enters the pipeline on every cycle.

Of course, a "single-cycle" instruction actually takes five cycles to complete, but they are

called single cycle because with this type of instruction the processor can complete one

instruction per cycle after the initial five-cycle delay.

AT697F bảng dữ liệu(PDF) 13 Page - ATMEL Corporation