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AT697F bảng dữ liệu(PDF) 25 Page - ATMEL Corporation

tên linh kiện AT697F
Giải thích chi tiết về linh kiện  SPARC V8 High Performance Low-power 32-bit Architecture
PDF  176 Pages
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nhà sản xuất  ATMEL [ATMEL Corporation]
Trang chủ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697F bảng dữ liệu(HTML) 25 Page - ATMEL Corporation

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AT697F
7703E–AERO–08/11
Each I/O interrupt is controlled through 4 parameters in the appropriate configuration
register (n = 1 & x in [0:3] or n = 2 & x in [4:7]):
•
the interrupt can be enabled or disabled (IOITn.enx)
•
the interrupt source can be chosen among PIO[15:0] and D[15:0](1)
(IOITn.iselx)
•
the interrupt can be level-triggered(2) or edge-triggered(2) (IOITn.lex)
•
the interrupt polarity can be high/low(2) when level-triggered or rising/falling(2) when
edge-triggered (IOITn.plx)
Notes: 1. D[15:0] can be used as part of the general-purpose I/O interface only when all the
memory areas (ROM, SRAM & I/O) are 8-bit wide and the SDRAM interface is not
enabled.
2. Whatever the chosen trigger mode, the I/O inputs are sampled on the rising edge of
the system clock. If generated synchronously, the signal driving the I/O interrupt shall
meet the required setup and hold constraints (see "Electrical Characteristics"). If gen-
erated asynchronously, the signal driving the I/O interrupt shall be maintained for a
minimum of 1.5 clock cycles so at least 1 active sample can be made.
The following table summarizes the I/O interrupt trigger configurations.
Table 6. I/O Interrupt Trigger Configuration
0
0
low level
0
1
high level
1
0
falling edge
1
1
rising edge
IOITn.lex
IOITn.plx
Trigger



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