HMS87C1202A datasheet(64/88 Pages) HYNIX

64 / 88 page

HMS87C130XA/120XA/110XA

Apr. 2001 ver1.0

flows when the input level is stable at the power voltage

level (VDD/VSS), however, when the input level gets high-

er than the power voltage level (by approximately 0.3 to

0.5V), a current begins to flow. Therefore, if cutting off the

output transistor at an I/O port puts the pin signal into the

high-impedance state, a current flow across the ports input

transistor, requiring to fix the level by pull-up or other

means.

Release the STOP mode

The exit from STOP mode is hardware reset or external in-

terrupt. Reset re-defines all the Control registers but does

not change the on-chip RAM. External interrupts allow

both on-chip RAM and Control registers to retain their val-

ues.

After releasing STOP mode, instruction execution is divid-

ed into two ways by I-flag(bit2 of PSW).

If I-flag = 1, the normal interrupt response takes place. If I-

flag = 0, the chip will resume execution starting with the

instruction following the STOP instruction. It will not vec-

tor to interrupt service routine. (refer to Figure 17-1)

When exit from Stop mode by external interrupt, enough

oscillation stabilization time is required to normal opera-

tion. Figure 17-2 shows the timing diagram. When release

the Stop mode, the Basic interval timer is activated on

wake-up. It is increased from 00H until FFH. The count

overflow is set to start normal operation. Therefore, before

STOP instruction, user must be set its relevant prescaler di-

vide ratio to have long enough time (more than 20msec).

This guarantees that oscillator has started and stabilized.

By reset, exit from Stop mode is shown in Figure 17-3.

Minimizing Current Consumption in Stop Mode

The Stop mode is designed to reduce power consumption.

To minimize the current consumption during Stop mode,

the user should turn-off output drivers that are sourcing or

sinking current, if it is practical. Weak pull-ups on port

pins should be turned off, if possible. All inputs should be

either as VSS or at VDD (or as close to rail as possible).

An intermediate voltage on an input pin causes the input

buffer to draw a significant amount of current.

Figure 17-1 STOP Releasing Flow by Interrupts

Figure 17-2 Timing of STOP Mode Release by External Interrupt

IEXX

STOP

INSTRUCTION

STOP Mode

Interrupt Request

STOP Mode Release

I-FLAG

Interrupt Service Routine

INSTRUCTION

Master Interrupt

Enable Bit PSW[2]

Corresponding Interrupt

Enable Bit (IENH, IENL)

STOP Mode

Normal Operation

Oscillator

(XIN pin)

N+1

N+2

N-1

N-2

Clear Basic Interval Timer

STOP Instruction Execution

Normal Operation

Stabilization Time

tST > 20mS

Internal

Clock

External

Interrupt

BIT

Counter

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