HMS87C1202A datasheet(57/88 Pages) HYNIX

57 / 88 page

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

15. INTERRUPTS

The HMS87C1X0XA interrupt circuits consist of Interrupt

enable register (IENH, IENL), Interrupt request flags of

IRQH, IRQL, Interrupt Edge Selection Register (IEDS),

priority circuit and Master enable flag(“I” flag of PSW).

The configuration of interrupt circuit is shown in Figure

15-1and Interrupt priority is shown in Table 15-1.

The External Interrupts INT0 and INT1 can each be transi-

tion-activated (1-to-0, 0-to-1 and both transition).

The flags that actually generate these interrupts are bit

INT0IF and INT1IF in Register IRQH. When an external

interrupt is generated, the flag that generated it is cleared

by the hardware when the service routine is vectored to

only if the interrupt was transition-activated.

The Timer 0 and Timer 1 Interrupts are generated by T0IF

and T1IF, which are set by a match in their respective tim-

er/counter register. The AD converter Interrupt is generat-

ed by ADIF which is set by finishing the analog to digital

conversion. The Watch dog timer Interrupt is generated by

WDTIF which set by a match in Watch dog timer register

(when the bit WDTON is set to “0”). The Basic Interval

Timer Interrupt is generated by BITIF which is set by a

overflowing of the Basic Interval Timer Register(BITR).

Figure 15-1 Block Diagram of Interrupt Function

BIT

BITIF

WDTIF

WDT

A/D Converter

Timer 1

Timer 0

External Int. 1

External Int. 0

IENH

Interrupt Enable

IRQH

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master

Enable Flag

I Flag

IENL

I-flag is in PSW, it is cleared by “DI”, set by

“EI” instruction.When it goes interrupt service,

I-flag is cleared by hardware, thus any other

interrupt are inhibited. When interrupt service is

completed by “RETI” instruction, I-flag is set to

“1” by hardware.

INT0IF

INT1IF

T0IF

T1IF

ADIF

IEDS

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