AT89LP51RC2 datasheet(54/254 Pages) ATMEL

54 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

7.4

Hardware Watchdog Reset

When the Hardware Watchdog times out, it will generate a reset pulse lasting 49 clock cycles.

By default this pulse is also output on the RST pin. The output pulse is either open-drain or

open-source as shown in Figure 7-4. In order to properly propagate this pulse to the rest of the

board in the case of an external capacitor or power-supply supervisor circuit, a 1 k

Ω resistor

should be placed in series with any external driving circuitry as shown in Figure 7-5. To disable

the RST output the DISRTO bit in the WDTPRG register must be set to one. Watchdog reset will

set the WDTOVF flag in WDTPRG. To prevent a Watchdog reset, the watchdog reset sequence

1EH/E1H must be written to WDTRST before the Watchdog times out. See Section 16. on page

104 for details on the operation of the Watchdog.

Figure 7-5.

Recommended Reset Output Schematics

7.5

PCA Watchdog Reset

Module 4 of the Programmable Counter Array (PCA) can be configured as a watchdog timer.

When a compare match occurs between module 4 and the PCA timer, it will generate an internal

reset pulse lasting 16 clock cycles. This pulse is never output on the RST pin. See Section 15.7

on page 104 for details on the operation of the PCA Watchdog.

7.6

Software Reset

The CPU may generate a 49-clock cycle reset pulse by writing the software reset sequence

5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDTPRG. See

“Software Reset” on page 105 for more information on software reset. Writing any sequences

other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and set both

WDTOVF and SWRST to flag an error. Software reset will also drive the RST pin active unless

DISRTO is set.

RST

POL = 1

AT89LP51xD2

To other

on-board

circuitry

1 k

Vcc

RST

Vcc

RST

POL = 0

AT89LP51xD2

To other

on-board

circuitry

1 k

RST

Vcc

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