AT89LP51RC2 datasheet(80/254 Pages) ATMEL

80 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

13.2

Mode 0 – Variable Width Timer/Counter

Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from

1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.

By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.

Figure 13-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count

rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counter input is enabled

to the Timer when TR1 = 1 and either GATE1 = 0 or INT1 =1. Setting GATE1 = 1 allows the

Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a

control bit in the TCON register. GATE1 is in TMOD. The 13-bit register consists of all 8 bits of

TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be

ignored. Setting the run flag (TR1) does not clear the registers.

The following equation gives the timeout period for Mode 0. In Fast Mode, TPS applies only

when the TnX2 bits in CKCON0 are set. TPS always applies in Compatibility Mode, therefore

setting TnX2 in Compatibility Mode will double the timeout period.

Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0, GATE0 and

INT0 replace the corresponding Timer 1 signals in Figure 13-1. There are two different C/T bits,

one for Timer 1 (TMOD.6) and one for Timer 0 (TMOD.2).

Table 13-4.

TCONB

– Timer/Counter Control Register B

TCONB = 91H

Reset Value = 0010 0100B

Not Bit Addressable

PWM1EN

PWM0EN

PSC12

PSC11

PSC10

PSC02

PSC01

PSC00

Bit

543

Symbol

Function

PWM1EN

Pulse Width Modulation 1 Enable

Set to configure Timer 1 for Pulse Width Modulation output on T1 (P3.5). Clear to disable T1 as an output.

PWM0EN

Pulse Width Modulation 0 Enable

Set to configure Timer 0 for Pulse Width Modulation output on T0 (P3.4). Clear to disable T0 as an output.

PSC12

PSC11

PSC10

Timer 1 Prescaler

Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1. After reset PSC1 = 100B which

enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89C51RB2/RC2/IC2.

PSC02

PSC01

PSC00

Timer 0 Prescaler

Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1. After reset PSC0 = 100B which

enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C51RB2/RC2/IC2.

Mode 0:

Time-out Period

256

PSCn

fSYS

-----------------------------------------

TPS

()

AT89LP51RC2 bảng dữ liệu(PDF) 80 Page - ATMEL Corporation

AT89LP51RC2 bảng dữ liệu(HTML) 80 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL