ML7344J datasheet(117/151 Pages) ETC2

117 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

117/151

(3) FIFO mode (65 byte or more)

The Host must read RX data from the RX_FIFO while checking INT[5] (group1: FIFO-Full interrupt) and

INT[4] (group1: FIFO-Empty interrupt) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operations

are identical to the FIFO mode (less than 64byte).

Yes

FIFO-FULL (INT[5])?

[INT_SOURCE_GRP1: B0 0x0D(5)]

INT[5] clear

[INT_SOURCE_GRP1: B0 0x0D]

Yes

RX FIFO-Full level Disable setting

[RX_FIFO_THRH: B0 0x19]

START

Read RX data from FIFO

[RD FIFO:B0 0x7F]

RX completion (INT[8])?

[INT_SOURCE_GRP2: B0 0x0E(0)]

INT[8] clear

[INT_SOURCE_GRP2: B0 0x0E(0)]

Yes

TRX_OFF issue

[RF_STATUS: B0 0x0B]

TX?

TX_ON issue

[RF_STATUS: B0 0x0B]

Yes

Set TX_ON after RX completion?

[RF_STATUS_CTRL:B0 0x0A]

Yes

Set TRX_OFF/SLEEP after RX completion?

[RF_STATUS_CTRL:B0 0x0A]

Yes

To RF state transition wait

flow

To RF state transition wait flow

To RF state transition wait

flow and TX flow

RX_ON issue *1

[RF_STATUS: B0 0x0B]

ACK_TX?

To ACK_TX flow

RX FIFO-Full level Enable setting

[RX_FIFO_THRH: B0 0x19]

RX FIFO pointer clear

[STATE_CLR: B0 0x16(1)]

INT[9] clear

[INT_SOURCE_GRP2: B0 0x0E(1)]

Read RX data

[RD_FIFO:B0 0x7F]

Next packet to be received ?

CRC error (INT[9])?

[INT_SOURCE_GRP2: B0 0x0E(1)]

*1 At lease following 2 interrupts in the group 2

should be un-masked for data receiving.

INT[8]: RX completion interrupt

INT[15]: Sync error interrupt

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