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ML7344J bảng dữ liệu(PDF) 115 Page - List of Unclassifed Manufacturers |
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ML7344J bảng dữ liệu(HTML) 115 Page - List of Unclassifed Manufacturers |
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115 / 151 page ![]() FEDL7344C/E/J-04 ML7344C/E/J 115/151 ○DIO output mode 2 operation While RXDIO_CTRL[1:0]=0b11, RX data (after L-field) will be stored into the RX_FIFO. RX data stored in the RX_FIFO is output through DIO pins, if setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1. Upon outputting RX data defined by L-field, RX is completed and generate RF completion interrupt (INT[8] group2). In case of TRX_OFF, issuing TRX_OFF by [RF_STATUS:B0 0x0B] register. *3: Please refer to RF state transition wait flow *2: Preamble, SyncWord and Error tolerance are set by following registers. Preamble [DATA_SET1: B0 0x07] [SYNC_CONDITION1-3: B0 0x45-47] SyncWord [SYNCWORD1_SET0-3: B1 0x27-2A] [SYNCWORD2_SET0-3: B1 0x2B-2E] [SYNC_WORD_LEN: B1 0x25] [DATA_SET2: B0 0x08] *5 RX data must be transferred to the HOST at rising edge of DCLK. *1 DIO/DCLK pins are defined as follows: [GPIO0_CTRL: B0 0x4E] [GPIO1_CTRL: B0 0x4F] [GPIO2_CTRL: B0 0x50] [GPIO3_CTRL: B0 0x51] [EXT_CLK_CTRL: B0 0x52] [SPI/EXT_PA_CTRL: B0 0x53] Preamble/SyncWord Error tolerance setting *2 START RX_ON issue *3 [RF_STATUS: B0 0x0B] No Yes TRX_OFF issue [RF_STATUS: B0 0x0B] Read RX data *5 (DIO pins) Yes Next packet to be RX? RXDIO_CTRL setting=0b11 [DIO_SET: B0 0x0C(7-6)] DIO_START =0b1 [DIO_SET:0B 0x0C(0)] No Yes SyncWord Detection (INT[13])? [INT_SOURCE_GRP3: B0 0x0F(5)] No To RF state transition wait flow DCLK output? (DCLK function pin) No Yes Wait *4 *4 Wait time should be more than Length field + 1 byte data receiving period. 1 byte data is decoded 8 bit data. If using Manchester code, 1 byte period becomes 160 μs (@ 100kbps). DIO pins setting *1 RX completion (INT[8])? [INT_SOURCE_GRP2: B0 0x0E(0)] |
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