ADC10D040CIVSSLASHNOPB datasheet(6/32 Pages) TI1

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ADC10D040

SNAS149G – OCT 2001 – REVISED MARCH 2013

www.ti.com

Converter Electrical Characteristics

The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN

(a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.

Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C

(1)

Units

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

(Limits)

STATIC CONVERTER CHARACTERISTICS

INL

Integral Non-Linearity

±0.65

±1.9

LSB (max)

+1.2

LSB (max)

DNL

Differential Non-Linearity

±0.35

−1.0

LSB (min)

Resolution with No Missing Codes

Bits

LSB (max)

Without Offset Correction

−3.3

−12

LSB (min)

VOFF

Offset Error

+1.5

LSB (max)

With Offset Correction

+0.4

−0.5

LSB (min)

%FS (max)

Gain Error

−4

−12

%FS (min)

DYNAMIC CONVERTER CHARACTERISTICS

fIN = 4.43 MHz, VIN = FSR −0.1 dB

9.5

Bits

ENOB

Effective Number of Bits

fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C

9.5

9.1

Bits (min)

fIN = 19.7 MHz, VIN = FSR −0.1 dB

9.4

Bits

fIN = 4.43 MHz, VIN = FSR −0.1 dB

SINAD

Signal-to-Noise Plus Distortion Ratio

fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C

56.3

dB (min)

fIN = 19.7 MHz, VIN = FSR −0.1 dB

fIN = 4.43 MHz, VIN = FSR −0.1 dB

SNR

Signal-to-Noise Ratio

fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C

57.3

dB (min)

fIN = 19.7 MHz, VIN = FSR −0.1 dB

fIN = 4.43 MHz, VIN = FSR −0.1 dB

−70

THD

Total Harmonic Distortion

fIN = 10.4 MHz, VIN = FSR −0.1 dB, TA = 25°C

−69

−61

dB (min)

fIN = 19.7 MHz, VIN = FSR −0.1 dB

−67

fIN = 4.43 MHz, VIN = FSR −0.1 dB

−86

HS2

Second Harmonic

fIN = 10.4 MHz, VIN = FSR −0.1 dB

−83

fIN = 19.7 MHz, VIN = FSR −0.1 dB

−81

fIN = 4.43 MHz, VIN = FSR −0.1 dB

−73

HS3

Third Harmonic

fIN = 10.4 MHz, VIN = FSR −0.1 dB

−73

fIN = 19.7 MHz, VIN = FSR −0.1 dB

−72

fIN = 4.43 MHz, VIN = FSR −0.1 dB

SFDR

Spurious Free Dynamic Range

fIN = 10.4 MHz, VIN = FSR −0.1 dB

fIN = 19.7 MHz, VIN = FSR −0.1 dB

fIN1 < 8.5 MHz, VIN = FSR −6.1 dB

IMD

Intermodulation Distortion

fIN2 < 9.5 MHz, VIN = FSR −6.1 dB

Overrange Output Code

(VIN+−VIN−) > 1.5V

1023

Underrange Output Code

(VIN+−VIN−) < −1.5V

FPBW

Full Power Bandwidth

140

MHz

(1)

The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables.

(2)

Typical figures are at TJ = 25°C, and represent most likely parametric norms.

(3)

Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is specified only at VREF = 1.4V and a clock duty

cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are

performed and limits specified with clock low and high levels of 0.3V and VD−0.3V, respectively.

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