UM809JS datasheet(7/15 Pages) UNIONSEMI

7 / 15 page

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http://www.union-ic.com

Rev.04 Dec.2013

7/15

UM809/810

Detailed Description

A microprocessor’s (µP’s) reset input starts the µP in a known state. The UM809/810 assert reset

to prevent code-execution errors during power-up, power-down, or brownout conditions. They

assert a reset signal whenever the VCC supply voltage declines below a preset threshold, keeping it

asserted for at least 140ms after VCC has risen above the reset threshold. The UM809/810 have a

push-pull output stage.

Applications Information

VCC Transient Rejection

In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions,

the UM809/810 are relatively immune to short-duration negative-going VCC transients (glitches).

Figure 7 shows typical transient duration vs. reset comparator overdrive, for which the

UM809/810 do not generate a reset pulse. The graph was generated using a negative-going pulse

applied to VCC, starting 0.5V above the actual reset threshold and ending below it by the

magnitude indicated (reset comparator overdrive). The graph indicates the maximum pulse width

a negative-going VCC transient can have without causing a reset pulse. As the magnitude of the

transient increases (goes farther below the reset threshold), the maximum allowable pulse width

decreases. Typically, for the UM8_L and UM8_M, a VCC transient that goes 100mV below the

reset threshold and lasts 20µs or less will not cause a reset pulse. A 0.1µF bypass capacitor

mounted as close as possible to the VCC pin provides additional transient immunity.

Figure 7. Maximum Transient Duration vs Overdrive for Glitch Rejection at 25℃

Output signal integrity during power down

When VCC falls below 1V, the UM809 RESET

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output no longer sinks current—it becomes an

open circuit. Therefore, high-impedance CMOS logic inputs connected to RESET

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can drift to

undetermined voltages. This presents no problem in most applications since most µP and other

circuitry is inoperative with VCC below 1V. However, in applications where RESET

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must be

valid down to 0V, adding a pull-down resistor to RESET

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causes any stray leakage currents to

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