DS2154 datasheet(14/87 Pages) DALLAS

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DS2154

14 of 87

Eight Times Clock [8XCLK]. 16.384 MHz clock that is frequency locked to the 2.048 MHz clock

provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from

the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via the

TEST2 register if not needed.

Line Interface Connect [LIUC]. Tie low to separate the line interface circuitry from the

framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/ RCLKI pins. Tie high

to connect the line interface circuitry to the framer/formatter circuitry and deactivate the

TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI

pins.

When

LIUC

tied

high,

the

TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be tied low.

Receive Tip and Ring [RTIP and RRING]. Analog inputs for clock recovery circuitry. These pins

connect via a 1:1 transformer to either the E1 line. See Section 12 for an example.

Transmit Tip and Ring [TTIP and TRING]. Analog line driver outputs. These pins connect via a

1:1.15 or 1:1.36 step-up transformer to the E1 line. See Section 12 for an example.

SUPPLY PINS

Digital Positive Supply [DVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and TVDD pins.

Receive Analog Positive Supply [RVDD]. 5.0 volts ± 5%. Should be tied to the DVDD and TVDD pins.

Transmit Analog Positive Supply [TVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and DVDD

pins.

Digital Signal Ground [DVSS]. 0.0 volts. Should be tied to the RVSS and TVSS pins.

Receive Analog Signal Ground [RVSS]. 0.0 volts. Should be tied to the DVSS and TVSS pins.

Transmit Analog Ground [TVSS]. 0.0 volts. Should be tied to the RVSS and DVSS pins.

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