AT45DB021D_13 datasheet(32/48 Pages) ETC2

32 / 48 page

3638M–DFLASH–5/2013

AT45DB021D

Figure 16-2. Output Test Load

17.

AC Waveforms

Six different timing waveforms are shown on page 32. Waveform 1 shows the SCK signal being low when CS

makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low

transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as

tWL). Timing waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 66MHz. Waveforms 1

and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.

Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to

waveform 1 and waveform 2, except that output SO is not restricted to become valid during the tWL period. These

timing waveforms are valid over the full frequency range (maximum frequency = 66MHz) of the RapidS serial case.

Figure 17-1. Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz)

Figure 17-2. Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66MHz)

DEVICE

UNDER

TEST

30pF

SCK

tCSS

VALID IN

tSU

tWH

tWL

tCSH

tCS

HIGH IMPEDANCE

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

SCK

tCSS

VALID IN

tSU

tWL

tWH

tCSH

tCS

HIGH Z

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

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