CS5101A datasheet(19/40 Pages) CIRRUS

19 / 40 page

calibration cycle on th e CS5102A takes

2,882,040 master clock cycles to complete (ap-

proximately 1.8 seconds with a 1.6 MHz master

clock). The CS5101A’s and CS5102A’s STBY

output remains low throughout the calibration se-

quence, and a rising transition indicates the

device is ready for normal operation. While cali-

brating, the CS5101A and CS5102A will ignore

changes on the HOLD input.

To perform the reset function, a simple power-on

reset circuit can be built using a resistor and ca-

pacitor as shown in Figure 8. The resistor should

be less than or equal to 10 k

Ω. The system power

supplies, voltage reference, and clock should all

be established prior RST rising.

Single-Channel Operation

The CS5101A and CS5102A can alternatively be

used to sample one channel by tying the CH1/2

input high or low. The unused AIN pin should be

tied to the analog input signal or to AGND. (If

operating in free run mode, AIN1 and AIN2 must

VA+

VD+

+5VA

4.7

µF

0.1

µF

0.1

µF

-5VA

4.7

µF

0.1

µF1 µF

0.1

µF

0.1

µF

VA-

VD-

REFBUF

CLKIN

XOUT

DGND

SLEEP

STBY

TRK1

TRK2

SSH/SDL

SDATA

RST

CH1/2

SCLK

HOLD

10 M

EXT

CLOCK

C2 = C1

Data

Interface

Control

Logic

CRS/FIN

CODE

SCKMOD

OUTMOD

BP/UP

VD+

Mode Control

AIN1

AIN2

1 nF

Analog

Sources

VREF

AGND

Voltage Reference

* For best dynamic

S/(N+D) performance.

NPO

Unused Logic inputs should

be tied to VD+ or DGND.

CS5101A

CS5102A

XTAL

XTAL & C1 Table

CS5101A

FRN

CS5102A

FRN

XTAL

8.0 MHz

8.192 MHz

1.6 MHz

C1, C2

10 pF

30 pF

2.0 MHz

1.6 MHz

TST

PDT, RBT,

SSC

PDT, RBT,

SSC

Figure 7. CS5101A/CS5102A System Connection Diagram

CS5101A CS5102A

DS45F2

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