CS5101A datasheet(6/40 Pages) CIRRUS

6 / 40 page

Notes: 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,

internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling

edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will

not exceed 1 master clock cycle + 140 ns.

20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625

µs of fine charge.

FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625

µs with an 1.6 MHz

clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may

be less than 9 clock cycles.

21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions

affecting acquisition and conversion times, as described above.

22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.

23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection

improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply

rejection versus frequency.

CS5102A

ANALOG CHARACTERISTICS (continued)

CS5102A -J,K

CS5102A -A,B

Parameter*

Symbol Min

Typ Max Min

Typ Max

Units

Specified Temperature Range

0 to +70

40 to +85

°C

Analog Input

Aperture Time

Aperture Jitter

100

Input Capacitance

(Note 6)

Unipolar Mode

Bipolar Mode

320

200

425

265

320

200

425

265

Conversion & Throughput

Conversion Time

(Note 19)

40.625

µs

Acquisition Time

(Note 20)

9.375

µs

Throughput

(Note 21)

ftp

kHz

Power Supplies

Power Supply Current

(Note 22)

Positive Analog

Negative Analog

(SLEEP High)

Positive Digital

Negative Digital

IA+

IA-

ID+

ID-

2.4

-2.4

2.5

-1.5

3.5

-3.5

3.5

-2.5

2.4

-2.4

2.5

-1.5

3.5

-3.5

3.5

-2.5

Power Consumption

(Notes 11, 22)

(SLEEP High)

(SLEEP Low)

Pdo

Pds

Power Supply Rejection:

(Note 23)

Positive Supplies

Negative Supplies

PSR

Typ. Power (mW) CLKIN (MHz)

0.8

1.0

1.2

1.4

1.6

DS45F2

CS5101A bảng dữ liệu(PDF) 6 Page - Cirrus Logic

CS5101A bảng dữ liệu(HTML) 6 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

bảng dữ liệu tải về

Link URL