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R5F64112DFB bảng dữ liệu(PDF) 62 Page - Renesas Technology Corp |
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R5F64112DFB bảng dữ liệu(HTML) 62 Page - Renesas Technology Corp |
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62 / 102 page ![]() R01DS0062EJ0130 Rev.1.30 Page 62 of 93 Mar 3, 2014 R32C/111 Group 5. Electrical Characteristics Note: 1. This value is applicable only when the main clock oscillation is stable. Note: 1. The recovery time from stop mode does not include the main clock oscillation stabilization time. The CPU starts operating before the oscillator is stabilized. Figure 5.4 Clock Circuit Timing Table 5.12 Electrical Characteristics of Oscillator (VCC1 =VCC2 = 3.0 to 5.5 V, VSS =0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement Condition Value Unit Min. Typ. Max. fSO(PLL) PLL clock self-oscillation frequency 35 55 80 MHz tLOCK(PLL) PLL lock time (1) 1ms tjitter(p-p) PLL jitter period (p-p) 2.0 ns f(OCO) On-chip oscillator frequency 62.5 125 250 kHz Table 5.13 Electrical Characteristics of Clock Circuitry (VCC1 =VCC2 = 3.0 to 5.5 V, VSS =0 V, and Ta =Topr, unless otherwise noted) Symbol Characteristics Measurement Condition Value Unit Min. Typ. Max. trec(WAIT) Recovery time from wait mode to low power mode 225 µs trec(STOP) Recovery time from stop mode (1) 225 µs t rec(STOP) Interrupt for exiting stop mode CPU clock Main clock oscillator output On-chip oscillator output Sub clock oscillator output On-chip oscillator output t rec(WAIT) Interrupt for exiting wait mode CPU clock Recovery time from stop mode t rec(STOP) Recovery time from wait mode to low power mode t rec(WAIT) |
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