SCF5250LPV100 datasheet(19/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

3.18

Debug and Test Signals

These signals interface with external I/O to provide processor debug and status signals.

3.18.1

Test Mode

The TEST[2:0] inputs are used for various manufacturing and debug tests. For normal mode TEST [2:1]

should be ways be tied low. TEST0 should be set high for BDM debug mode and set low for JTAG mode.

3.18.2

High Impedance

The assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z is

independent of the clock.

NOTE

JTAG operation will override the HI_Z pin.

3.18.3

Processor Clock Output

The internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output that

is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The

PSTCLK/GPIO51 is at the same frequency as the core processor.

3.18.4

Debug Data

The debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,

DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displays

captured processor data and break-point status.

3.18.5

Processor Status

The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and

PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is

synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.

Table 12 shows the encodings of these signals.

SCF5250LPV100 bảng dữ liệu(PDF) 19 Page - Freescale Semiconductor, Inc