SCF5250LPV100 datasheet(34/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Figure 11 provides the IEEE 1149.1 JTAG timing diagram and Table 30 provides the timing parameters.

Figure 11. JTAG AC Timing Diagram

Table 30. JTAG AC Timing Specifications

Num

Characteristic

Min

Max

Units

–

TCK Frequency of Operation

MHz

TCK Cycle Time

100

–

J2a

TCK Clock Pulse High Width

–

J2b

TCK Clock Pulse Low Width

–

J3a

TCK Fall Time (VIH=2.4 V to VIL=0.5 V)

–

J3b

TCK Rise Time (VIL=0.5 v to VIH=2.4 V)

–

TDI, TMS to TCK rising (Input Setup)

–

TCK rising to TDI, TMS Invalid (Hold)

–

Boundary Scan Data Valid to TCK (Setup)

tbd

–

TCK to Boundary Scan Data Invalid to rising edge (Hold)

tbd

–

TRST Pulse Width (asynchronous to clock edges)

–

TCK falling to TDO Valid (signal from driven or three-state)

–

J10

TCK falling to TDO High Impedance

–

J2A

J2B

J10

J11

J12

J3A

J3B

TCK

TDI, TMS

TRST

TDO

BOUNDARY

SCAN DATA

OUTPUT

BOUNDARY

SCAN DATA

INPUT

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