SCF5250LPV100 datasheet(27/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Figure 4. Input/Output AC Timing Definition-III

Table 21. Input AC Timing Specification

Num

Characteristic

Min

Max

Units

B11,2

1 Inputs (rising): DATA[31:16]

2 AC timing specs assume 40pF load capacitance on BCLK and 50pF load capacitance on output pins. If this value is different,

the input and output timing specifications would need to be adjusted to match the clock load.

Signal Valid to BCLK Rising (setup)

–

B21

BCLK Rising to signal Invalid (hold)

–

B31

BCLK to Input High Impedance

–

BCLK cycle

Table 22. Output AC Timing Specification

Num

Characteristic1

Min

Max

Units

B102

BCLK (8mA) Rising to signal Valid

–

B112

BCLK (8mA) Rising to signal Invalid (hold)

3.5

–

B103

BCLK (4mA) Rising to signal Valid

–

B113

BCLK (4mA) Rising to signal Invalid (hold)

–

B124

BCLK to High Impedance (Three-State)

–

B13

B14

BCLK

HIZ

OUTPUTS

BCLK

INPUTS

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