AS8506 datasheet(5/89 Pages) AMSCO

5 / 89 page

ams Datasheet, Confidential:2013-Sep [1-00]

AS8506 – 5

P i n A ssig n men t

Figure 4:

Pin Description

Pin Number

Pin Name

Pin Type

Description

1TSECH

Analog input /

output

Flyback converter transformer secondary high side

TSECL

Flyback converter transformer secondary low side

VCELL7

Battery cell 7 high level pin

VCELL6

Battery cell 6 high level pin

VCELL5

Battery cell 5 high level pin

VCELL4

Battery cell 4 high level pin

VCELL3

Battery cell 3 high level pin

VCELL2

Battery cell 2 high level pin

VCELL1

Battery cell 1 high level pin

C-GND

Power supply

input

Battery cell 1 low level pin

Not connected

VREF_IN

Analog input /

output

Cell voltage reference value (cell target voltage of

battery)

GND

Power supply

input

Ground to the IC

TRIG_IN

Digital input

This pin triggers the cell balancing in the device.

Short pulse is for receiving status and continuous

‘High’ for cell balancing. It also acts as a data line

during 3-wire communication.

CLK_IN

Clock input pin in the Slave device. This pin also acts

as a clock during 3-wire communication. Scan clock

in scan mode.

CVT_NOK_OUT

Digital output

This pin alerts when the cell voltage or the

device/cell temperature is not within limits. During

3-wire communication, the CRC error is indicated on

this pin. The internal device cell voltage or

temperature status is ORed with CVT_NOK_IN on

this pin.

BD_OUT

The ‘device internal balance done’ and ‘balance done

from above device’ are ANDed on this pin. This pin in

Master device indicates the complete system

balance done. During address allocation process,

this pin will be ‘High’ if BD_IN is ‘High’.

FD_OUT

Flyback converter gate/opto coupler drive (pad is

push-pull type) can drive up to 12mA.

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