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AS8506 bảng dữ liệu(PDF) 41 Page - ams AG

tên linh kiện AS8506
Giải thích chi tiết về linh kiện  Battery Cell Monitor and Balancer IC
PDF  89 Pages
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nhà sản xuất  AMSCO [ams AG]
Trang chủ  http://www.ams.com
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AS8506 bảng dữ liệu(HTML) 41 Page - ams AG

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ams Datasheet, Confidential:2013-Sep [1-00]
AS8506 – 41
Devic e I n te r f ac e
Figure 34:
SPI Block Write Operation with Negative Clock Polarity
SPI Read Operation
The SPI read operation also begins with clock polarity selection
at negative edge of SCSN (see Figure 30). Once the clock
polarity is selected, the SPI read command is given by providing
‘1’ in R/W bit of the header field in first sampling edge at SDI
pin. The next bit in header fields is reserved and set to ‘0’. The
6 bits address of register to be read is provided at SDI pin in
next six consecutive sampling edges of SCLK. The read data is
followed by last bit of header field on SDO pin. With each
sampling edge a bit can be read on SDO pin starting from MSB
to LSB. In case of multi-data bytes, MSB of next data byte can
be read after the LSB of previous data byte. During complete
SPI read operation the SCSN has to be ‘Low’. The SPI read
operation ends with positive edge of SCSN. The wave form for
SPI read operation with single data byte is shown in Figure 35
and Figure 36.
Figure 35:
SPI Read Operation with Negative Clock Polarity and 1 Byte of Data Field
CS
SCLK
SDI
SDO
00
A
1
A
4
A
2
A
3
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
Data D7-D0 is
moved to Address
A5-A0 here
Data D7-D0 is
moved to Address
A5-A0 +1 here
Data D7-D0 is
moved to Address
A5-A0 +2 here
Data D7-D0 is
moved to Address
A5-A0 +3 here
Data D7-D0 is
moved to Address
A5-A0 +4 here
A
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
7
D
6
D
0
A
5
D7
D6
D5
D4
D3
D2
D1
D0
R0
A4
A3
A2
A1
A0
SCLK
SDI
SDO
SCSN
A5



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