IO96NDB2V1 datasheet(141/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-125

Timing Characteristics

1.5 V DC Core Voltage

Table 2-202 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–1

Std.

Units

tCLKQ

Clock-to-Q of the Core Register

0.56

0.66

tSUD

Data Setup Time for the Core Register

0.44

0.51

tHD

Data Hold Time for the Core Register

0.00

tSUE

Enable Setup Time for the Core Register

0.46

0.55

tHE

Enable Hold Time for the Core Register

0.00

tCLR2Q

Asynchronous Clear-to-Q of the Core Register

0.41

0.48

tPRE2Q

Asynchronous Preset-to-Q of the Core Register

0.41

0.48

tREMCLR

Asynchronous Clear Removal Time for the Core Register

0.00

tRECCLR

Asynchronous Clear Recovery Time for the Core Register

0.23

0.27

tREMPRE

Asynchronous Preset Removal Time for the Core Register

0.00

tRECPRE

Asynchronous Preset Recovery Time for the Core Register

0.23

0.27

tWCLR

Asynchronous Clear Minimum Pulse Width for the Core Register

0.30

0.34

tWPRE

Asynchronous Preset Minimum Pulse Width for the Core Register

0.30

0.34

tCKMPWH

Clock Minimum Pulse Width High for the Core Register

0.56

0.64

tCKMPWL

Clock Minimum Pulse Width Low for the Core Register

0.56

0.64

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

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