IO96NDB2V1 datasheet(135/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-119

Timing Characteristics

1.5 V DC Core Voltage

Figure 2-34 • Output DDR Timing Diagram

910

tDDROREMCLR

tDDROHD1

tDDROREMCLR

tDDROHD2

tDDROSUD2

tDDROCLKQ

tDDRORECCLR

CLK

Data_R

Data_F

CLR

Out

tDDROCLR2Q

710

Table 2-198 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–1

Std.

Units

tDDROCLKQ

Clock-to-Out of DDR for Output DDR

0.72

0.84

tDDRISUD1

Data_F Data Setup for Output DDR

0.39

0.45

tDDROSUD2

Data_R Data Setup for Output DDR

0.39

0.45

tDDROHD1

Data_F Data Hold for Output DDR

0.00

tDDROHD2

Data_R Data Hold for Output DDR

0.00

tDDROCLR2Q

Asynchronous Clear-to-Out for Output DDR

0.82

0.96

tDDROREMCLR

Asynchronous Clear Removal Time for Output DDR

0.00

tDDRORECCLR

Asynchronous Clear Recovery Time for Output DDR

0.23

0.27

tDDROWCLR1

Asynchronous Clear Minimum Pulse Width for Output DDR

0.19

0.22

tDDROCKMPWH

Clock Minimum Pulse Width High for the Output DDR

0.31

0.36

tDDROCKMPWL

Clock Minimum Pulse Width Low for the Output DDR

0.28

0.32

FDDOMAX

Maximum Frequency for the Output DDR

250.00 250.00

MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

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