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IO96NDB2V1 bảng dữ liệu(PDF) 128 Page - Microsemi Corporation |
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IO96NDB2V1 bảng dữ liệu(HTML) 128 Page - Microsemi Corporation |
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128 / 242 page  ProASIC3L DC and Switching Characteristics 2-112 Revision 13 Timing Characteristics 1.5 V DC Core Voltage 1.2 V DC Core Voltage Table 2-190 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.60 0.71 ns tOSUD Data Setup Time for the Output Data Register 0.32 0.37 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.45 0.53 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 0.96 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.82 0.96 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-191 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.78 0.92 ns tOSUD Data Setup Time for the Output Data Register 0.42 0.49 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.58 0.69 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.07 1.26 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.07 1.26 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.30 0.35 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.30 0.35 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. |
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