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IO96NDB2V1 bảng dữ liệu(PDF) 113 Page - Microsemi Corporation |
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IO96NDB2V1 bảng dữ liệu(HTML) 113 Page - Microsemi Corporation |
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113 / 242 page ![]() ProASIC3L Low Power Flash FPGAs Revision 13 2-97 SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-166 • Minimum and Maximum DC Input and Output Levels SSTL3 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. VmA mA Max. mA1 Max. mA1 µA2 µA2 14 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 51 54 10 10 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-21 • AC Loading Table 2-167 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF) VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30 Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 30 pF 50 25 SSTL3 Class I VTT Table 2-168 • SSTL3 Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.59 2.08 0.04 1.81 0.38 2.11 1.65 2.11 1.65 ns –1 0.50 1.77 0.03 1.54 0.33 1.80 1.41 1.80 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-169 • SSTL3 Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.77 2.08 0.05 1.81 0.50 2.11 1.65 2.11 1.65 ns –1 0.66 1.77 0.04 1.54 0.43 1.80 1.41 1.80 1.41 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. |
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