IO96NDB2V1 datasheet(238/242 Pages) MICROSEMI

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Datasheet Information

5-6

Revision 13

Revision 4 (June 2008)

DC and Switching

Characteristics

Advance v0.3

Tables have been updated to include the LVCMOS 1.2 V I/O set.

DDR Tables have two additional data points added to reflect both edges for Input

DDR setup and hold time.

Power data table has been updated to match SmartPower data rather then

simulation values.

N/A

Table 2-1 • Absolute Maximum Ratings was updated to add VMV to the VCCI

parameter row and to remove the word "output" from the parameter description

for VCCI. Table note 3 was added.

2-1

Table 2-2 • Recommended Operating Conditions 1 was updated to add table note

references and rearrange the order of notes. VMV was added to the VCCI

parameter row. A new row was added for VCC, 1.5 V DC core supply voltage.

The table note stating that 1.5 V data will be released at a later date is new. The

table note on VMV pins is new.

2-2

Table 2-4 • Overshoot and Undershoot Limits 1. The title was revised to remove

"as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO

density over cycles." Table note 3 was revised to remove "refers only to

overshoot/undershoot limits for simultaneous switching I/Os.

2-3

EQ 2 was updated. The temperature was changed to 100°C, and therefore the

end result changed.

2-6

The table notes for Table 2-8 • Quiescent Supply Current (IDD) Characteristics,

ProASIC3L Flash*Freeze Mode* and Table 2-9 • Quiescent Supply Current (IDD)

Characteristics, ProASIC3L Sleep Mode* were updated to remove VMV and

include PDC6 and PDC7. The table note for Table 2-8 • Quiescent Supply Current

(IDD) Characteristics, ProASIC3L Flash*Freeze Mode* was updated to include

VJTAG.

2-7

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode is

new.

2-8

Note 2 of Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No

Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to

include PDC6 and PDC7.

2-8

Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software

Settings through Table 2-17 • Summary of I/O Output Buffer Power (per pin) –

Default I/O Software Settings 1were updated to change PDC2 to PDC6 and

PDC3 to PDC7. The table notes were updated to reflect that power was

measured on VCCI. The subtitle of the table was changed from "Applicable to

Advanced I/O Banks" to "Applicable to Pro I/O Banks."

2-9

through

2-12

The word "input" in the titles of Table 2-15 • Summary of I/O Output Buffer Power

(per pin) – Default I/O Software Settings 1 and Table 2-16 • Summary of I/O

Output Buffer Power (per pin) – Default I/O Software Settings 1, was changed to

"output."

2-11, 2-12

The value of CLOAD for single-ended 3.3 V PCI was changed to 10 from 5 in

Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software

Settings 1 through Table 2-17 • Summary of I/O Output Buffer Power (per pin) –

Default I/O Software Settings 1.

2-11

through

2-12

Revision

Changes

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