W25X05CLZPIG datasheet(23/51 Pages) WINBOND

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W25X05CL/10CL/20CL

Publication Release Date: March 23, 2012

- 23 -

Revision B

8.2.12

Continuous Read Mode Bits (M7-0)

The “Continuous Read Mode” bits are used in conjunction with the “Fast Read Dual I/O” instruction to

provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus

allow true XIP (execute in place) to be performed on serial flash devices.

M7-0 need to be set by the Dual I/O Read instruction. M5-4 are used to control whether the 8-bit SPI

instruction code BBh is needed or not for the next command. When M5-4 = (1,0), the next command

will be treated same as the current Dual I/O Read command without needing the 8-bit instruction code;

when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can be

accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.

8.2.13

Continuous Read Mode Reset (FFFFh)

Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the

Continuous Read Mode and return to normal SPI operation, as shown in figure 13.

Figure 13. Continuous Read Mode Reset for Fast Read Dual I/O

Since W25X05CL/10CL/20CL does not have a hardware Reset pin, so if the controller resets while

W25X05CL/10CL/20CL

are set

to Continuous

Mode Read,

the W25X05CL/10CL/20CL

will

not recognize any initial standard SPI instructions from the controller. To address this possibility, it is

recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a

system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard

SPI instructions to be recognized.

To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in

instruction “FFFFh”.

/CS

Mode 0

Mode 3

Mode 0

Mode 3

CLK

IO0

Mode Bit Reset

for Dual I/O

Don

’t Care

FFFFh

/CS

Mode 0

Mode 3

CLK

IO0

Don

’t Care

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