W25Q32FVZPIP datasheet(32/99 Pages) WINBOND

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W25Q32FV

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Figure 8b. Read Status Register Instruction (QPI Mode)

8.2.5

Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)

The Write Status Register instruction allows the Status Registers to be written. The writable Status

locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-

volatile OTP bits, once it is set to 1, it cannot be cleared to 0.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have

been executed for the device to accept the Write Status Register instruction (Status Register bit WEL

must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction

code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must

have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).

However, SRP1 and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these

bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit

values will be lost, and the non-volatile Status Register bit values will be restored.

During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven

high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC

Characteristics). While the Write Status Register cycle is in progress, the Read Status Register

instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the

Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions

again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status

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