W25Q32FVZPIP datasheet(13/99 Pages) WINBOND

13 / 99 page

W25Q32FV

Publication Release Date: Sept 16,, 2013

- 12 -

Revision H

FUNCTIONAL DESCRIPTIONS

6.1

SPI / QPI Operations

Figure 3. W25Q32FV Serial Flash Memory Operation Diagram

6.1.1

Standard SPI Instructions

The W25Q32FV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the

DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The

DO output pin is used to read data or status from the device on the falling edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is

not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and

rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

6.1.2

Dual SPI Instructions

The W25Q32FV supports Dual SPI operation when using instructions such as “Fast Read Dual Output

(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the

device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are

ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-

critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins

become bidirectional I/O pins: IO0 and IO1.

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