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TMS320DM6467CCUT6 bảng dữ liệu(HTML) 86 Page - Texas Instruments |
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86 / 355 page  TMS320DM6467 SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 www.ti.com 4.2 Power Considerations The DM6467 provides several means of managing power consumption. As described in the Section 7.3.4, DM6467 Power and Clock Domains, the DM6467 has one single power domain—the “Always On” power domain. Within this power domain, the DM6467 utilizes local clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see Section 7.3.5, Power and Sleep Controller (PSC) and the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9). Some of the DM6467 peripherals support additional power saving features. For more details on power saving features supported, see the peripheral-specific reference guides [listed/linked in the TMS320DM646x DMSoC Peripherals Overview Reference Guide (literature number SPRUEQ0). Most DM6467 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN register in the System Module (see Figure 4-1 ) is used to selectively power down unused 3.3-V I/O pins. Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers. For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see Section 4.7.3, Pin Multiplexing Details. Note: The VDD3P3V_PWDN register only controls the power to the I/O buffers. The Power and Sleep Controller (PSC) determines the clock/power state of the peripheral. 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED USBV CLKOUT RSV SPI VLYNQ RESERVED GMII MII MCASP1 MCASP0 PCIHPI1 PCIHPI0 R-000 R/W-1 R/W-0 R-0 R/W-1 R/W-1 R-00 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO WDTIM TIM23 TIM01 PWM1 PWM0 UR2FC UR2DAT UR1FC UR1DAT UR0MDM UR0DF VPIF3 VPIF2 VPIF1 VPIF0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-1. VDD3P3V_PWDN Register [0x01C4 0048] 86 Device Configurations Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 |
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