TMS320DM6467CCUT6 datasheet(65/355 Pages) TI1

65 / 355 page

TMS320DM6467

www.ti.com

SPRS403H – DECEMBER 2007 – REVISED JUNE 2012

3.7.21 UART2

Table 3-25. UART2 Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

UART2 WITH FLOW CONTROL (PINMUX1.UART2CTL = 00)

Actual UART2 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see

Section 4.7.3, Pin Multiplexing.

URXD2/

This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.

CRG1_VCXI/

IPD

When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)

AB20

I/O/Z

GP[39]/

DVDD33

and CRGEN0/1 are not enabled (PINMUX0.CRGMUX

≠ x01, 110), this pin is

CRG0_VCXI

UART2 receive data, URXD2 (I).

UTXD2/

This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.

URCTX2/

IPD

When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)

CRG1_PO/

AA19

I/O/Z

DVDD33

and CRGEN0/1 are not enabled (PINMUX0.CRGMUX

≠ x01, 110), this pin is

GP[40]/

UART2 transmit data, UTXD2 (O/Z).

CRG0_PO

This pin is multiplexed between UART2, TSIF0, and GPIO.

URTS2 /UIRTX2/

IPU

When UART2 UART with flow control muxing is selected (PINMUX1.UART2CTL =

TS0_PSTIN/

AC20

I/O/Z

DVDD33

00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART2

GP[41]

request-to-send, URTS2 (O/Z).

UCTS2 /USD2/

This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.

CRG0_VCXI/

IPU

When UART2 UART with flow control muxing is selected (PINMUX1.UART2CTL =

AC21

I/O/Z

GP[42]/

DVDD33

00) and TSIF1 output is not enabled (PINMUX0.PTSOMUX = 0x), this pin is

TS1_PSTO

UART2 clear-to-send, UCTS2 (I).

UART2 WITHOUT FLOW CONTROL (PINMUX1.UART2CTL = 01)

URXD2/

This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.

CRG1_VCXI/

IPD

When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)

AB20

I/O/Z

GP[39]/

DVDD33

and CRGEN0/1 are not enabled (PINMUX0.CRGMUX

≠ x01, 110), this pin is

CRG0_VCXI

UART2 receive data, URXD2 (I).

UTXD2/

This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.

URCTX2/

IPD

When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)

CRG1_PO/

AA19

I/O/Z

DVDD33

and CRGEN0/1 are not enabled (PINMUX0.CRGMUX

≠ x01, 110), this pin is

GP[40]/

UART2 transmit data, UTXD2 (O/Z).

CRG0_PO

UART2 IrDA/CIR FUNCTION (PINMUX1.UART2CTL = 10)

URXD2/

This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.

CRG1_VCXI/

IPD

When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)

AB20

I/O/Z

GP[39]/

DVDD33

and CRGEN0/1 are not enabled (PINMUX0.CRGMUX

≠ x01, 110), this pin is

CRG0_VCXI

UART2 receive data, URXD2 (I).

UTXD2/URCTX2/

This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.

CRG1_PO/

IPD

When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)

AA19

I/O/Z

GP[40]/

DVDD33

and CRGEN0/1 are not enabled (PINMUX0.CRGMUX

≠ x01, 110), this pin is the

CRG0_PO

UART2 CIR transmit data, URCTX2 (O/Z).

This pin is multiplexed between UART2, TSIF0, and GPIO.

URTS2/UIRTX2/

IPU

When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)

TS0_PSTIN/

AC20

I/O/Z

DVDD33

and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART2 IrDA

GP[41]

transmit data, UIRTX2 (O/Z).

UCTS2/USD2/

This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.

CRG0_VCXI/

IPU

When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)

AC21

I/O/Z

GP[42]/

DVDD33

and CRGEN0 on TSIF0 output is not enabled (PINMUX0.TSSOMUX = 0x), this

TS1_PSTO

pin is UART2 IrDA tranceiver control, USD2 (O/Z).

(1)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(2)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(3)

Specifies the operating I/O supply voltage for each signal

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