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TMS320DM6467CCUT6 bảng dữ liệu(PDF) 41 Page - Texas Instruments |
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TMS320DM6467CCUT6 bảng dữ liệu(HTML) 41 Page - Texas Instruments |
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41 / 355 page  TMS320DM6467 www.ti.com SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 Table 3-10. DDR2 Memory Controller Terminal Functions (continued) SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. DDR_D[31] Y20 DDR_D[30] W20 DDR_D[29] Y21 DDR_D[28] AA21 DDR_D[27] U21 DDR_D[26] T21 DDR_D[25] R20 DDR_D[24] T20 DDR_D[23] AB22 DDR_D[22] Y22 DDR_D[21] AA22 DDR_D[20] AA23 DDR_D[19] V23 DDR_D[18] U23 DDR_D[17] T22 DDR_D[16] U22 I/O/Z DVDDR2 DDR2 data bus can be configured as 32 bits wide or 16 bits wide. DDR_D[15] H22 DDR_D[14] G23 DDR_D[13] G22 DDR_D[12] F23 DDR_D[11] E23 DDR_D[10] C22 DDR_D[9] B22 DDR_D[8] C23 DDR_D[7] H20 DDR_D[6] G21 DDR_D[5] F21 DDR_D[4] G20 DDR_D[3] B21 DDR_D[2] C20 DDR_D[1] D20 DDR_D[0] C21 DDR_DQGATE0 J19 O/Z DVDDR2 DDR2 strobe gate signal for lower-half data bus DDR_DQGATE1 J21 I DVDDR2 DDR2 strobe gate signal return for lower-half data bus DDR_DQGATE2 R19 O/Z DVDDR2 DDR2 strobe gate signal for upper-half data bus DDR_DQGATE3 R21 I DVDDR2 DDR2 strobe gate signal return for upper-half data bus DDR_VREF P23 S (4) Reference voltage input for the SSTL_18 IO buffers. Impedance control for DDR2 outputs. This must be connected via a 50- Ω (±5% DDR_ZP L19 O (4) tolerance) resistor to VSS. Impedance control for DDR2 outputs. This must be connected via a 50- Ω (±5% DDR_ZN M19 O (4) tolerance) resistor to DVDDR2. (4) For more information, see the Recommended Operating Conditions table Copyright © 2007–2012, Texas Instruments Incorporated Device Overview 41 Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 |
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