MSP430F6776IPZ datasheet(75/157 Pages) TI

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SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

CKPL =0

CKPL =1

LOW/HIGH

1/f

UCxCLK

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

UCMODEx=01

UCMODEx=10

STE

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

Figure 13. SPI Master Mode, CKPH = 1

eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

2 V

tSTE,LEAD

STE lead time, STE low to clock

3 V

2 V

tSTE,LAG

STE lag time, Last clock to STE high

3 V

2 V

tSTE,ACC

STE access time, STE low to SOMI data out

3 V

2 V

STE disable time, STE high to SOMI high

tSTE,DIS

impedance

3 V

2 V

tSU,SI

SIMO input data setup time

3 V

2 V

tHD,SI

SIMO input data hold time

3 V

2 V

UCLK edge to SOMI valid,

tVALID,SO

SOMI output data valid time(2)

CL = 20 pF

3 V

2 V

tHD,SO

SOMI output data hold time(3)

CL = 20 pF

3 V

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 14 and Figure 15.

(3)

Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 14

and Figure 15.

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